Computer architecture is the combination of microarchitecture and instructionset Relation to instruction set architecture A microarchitecture organized arounda single bus The ISA is roughly the same as the programming model of aprocessor as seen by an assembly language programmer or compiler writer.

Some of these stages include instruction fetch, instruction decode, execute, andwrite back.

Microarchitectural concepts Instruction cycle Main article: instruction cycle Ingeneral, all CPUs, single-chip microprocessors or multi-chip implementationsrun programs by performing the following steps: Read an instruction anddecode it Find any associated data that is needed to process the instructionProcess the instruction Write the results out The instruction cycle is repeatedcontinuously until the power is turned off.

Instruction set choice Instruction sets have shifted over the years, fromoriginally very simple to sometimes very complex.

Such uniform instructions were easily fetched, decoded and executed in apipelined fashion and a simple strategy to reduce the number of logic levels inorder to reach high operating frequencies; instruction cache-memoriescompensated for the higher operating frequency and inherently low codedensity while large register sets were used to factor out as much of the memoryaccesses as possible.

Instruction pipelining Main article: instruction pipeline One of the first, and mostpowerful, techniques to improve performance is the use of the instructionpipeline.

Early processor designs would carry out all of the steps above for oneinstruction before moving onto the next.

Pipelines improve performance by allowing a number of instructions to worktheir way through the processor at the same time.

Although any one instruction takes just as long to complete the CPU as a wholeRetiresinstructions much faster.

From the time that the processor’s instruction decoder has figured out that ithas encountered a conditional branch instruction to the time that the decidingregister value can be read out, the pipeline needs to be stalled for severalcycles, or if it’s not and the branch is taken, the pipeline needs to be flushed.

The instruction issue logic grows in complexity by reading in a huge list ofinstructions from memory and handing them off to the different execution unitsthat are idle at that point.

Out-of-order execution allows that ready instruction to be processed while anolder instruction waits on the cache, then re-orders the results to make itappear that everything happened in the programmed order.

Register renaming Main article: Register renaming Register renaming refers to atechnique used to avoid unnecessary serialized execution of programinstructions because of the reuse of the same registers by those instructions.

One set of instructions is executed first to leave the register to the other set, but if the other set is assigned to a different similar register, both sets ofinstructions can be executed in parallel in series.